A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects

This article presents a quarter-rate source-synchronous PAM-4 receiver for energy-efficient chip-to-module communication. A novel single-stage multiple peaking continuous-time linear equalizer (MP-CTLE) using feedback enabled scheme both high-frequency equalization (HF-EQ) and low-frequency (LF-EQ) is proposed to improve the BER performance overall energy efficiency. The LF-EQ of MP-CTLE eliminates need many DFE taps in SR/VSR applications save power area. 1-tap feedforward (FFE) used further compensate loss. We also use ring oscillator based wide bandwidth phase-locked loop (WBW-PLL) as multiphase clock generator (MPCG) data recovery with acceptable phase accuracy. Fabricated 40-nm CMOS technology, prototype chip achieves error-free operation up 52 Gb/s superior bit efficiency 0.126pJ/bit/s/dB while compensating 7.3-dB channel loss at 13GHz. With MP-CTLE, extends from PRBS-7 PRBS-9. bathtub curve $10^{-6}$ improved 0.018 UI around 0.1 UI.